System Design as a Creative Mathematical Activity

This paper contributes to the understanding of rational systems design and verification. We give evidence that the rôle of mathematics in development and verification is not limited to useful calculations: Ideally, designing is a creative mathematical activity, which comprises finding a theorem, if necessary strengthening its assumptions until it can be proven. A canonical form of this ‘verification theorem’ is introduced and illustrated with informal and formal examples. Although for good reasons most systems are designed without use of formal methods it may be a source of useful insight to understand all design as an ‘approximation’ of such a mathematical activity. This leads amongst others to a taxonomy of design decisions, and it may help to relate paradigms, theories, methods, languages, and tools from different areas of computer science to each other to make optimal use of them

Timed Automaton Models for Simple Programmable Logic Controllers

We give timed automaton models for a class of Programmable Logic Controller (PLC) applications, that are programmed in a simple fragment of the language Instruction Lists as defined in the standard IEC 1131-3. Two different approaches for modelling timers are suggested, that lead to two different timed automaton models. The purpose of this work is to provide a basis for verification and testing of real-time properties of PLC applications. Our work can be seen in broader context: it is a contribution to methodical development of provably correct programs. Even if the present PLC hardware will be substituted by e.g. Personal Computers, with a similar operation mode, the development and verification method will remain useful

What is the method in applying formal methods to PLC applications?

The question we investigate is how to obtain PLC applications with confidence in their proper functioning. Especially, we are interested in the contribution that formal methods can provide for their development. Our maxim is that the place of a particular formal method in the total picture of system development should be made very clear. Developers and customers ought to understand very well what they can rely on or not, and we see our task in trying to make this explicit. Therefore, for us the answer to the question above leads to the following questions: Which parts of the system can be treated formally? What formal methods and tools can be applied? What does their successful application tell (or does not) about the proper functioning of the whole system

Design as the Discovery of a Mathematical Theorem - What designers should know about the art of mathematics

This paper tries to contribute to the understanding of the essence of rational systems design and verification. Information technologists and teachers and students of computer science may find the concepts presented here helpful to disentangle complex achievements of computer science and re-use their constituents in other contexts, but also to view their own activities in the light of other disciplines. First a consistent set of notions and a diagram and a formula are introduced, with respect to which important aspects of a rational design process can be understood, together with a proposal for a consistent terminology. Subsequently, formal definitions are provided for basic concepts of formal methods and a mathematical foundation for our formula. They shall illustrate that the rle of mathematics in development and verification is not limited to useful calculations: Ideally, designing is a creative mathematical activity, which comprises finding a theorem, if necessary strengthening its..

What is the method in applying formal methods to PLC applications?

The question we investigate is how to obtain PLC applications with confidence in their proper functioning. Especially, we are interested in the contribution that formal methods can provide for their development. Our maxim is that the place of a particular formal method in the total picture of system development should be made very clear. Developers and customers ought to understand very well what they can rely on or not, and we see our task in trying to make this explicit. Therefore, for us the answer to the question above leads to the following questions: Which parts of the system can be treated formally? What formal methods and tools can be applied? What does their successful application tell (or does not) about the proper functioning of the whole system

A Taxonomy for Computing Science -- To design is to invent a formally provable statement

We try to capture the essence of information technology and computing science, arguing that information technologists have the same principal goal as all technologists: to create machines with certain properties. To achieve this, they formalize the problem, i.e. abstract the properties into a specification and invent or develop a schema, i.e. an abstraction of the machine's structure. Subsequently, it is their principal task to prove that the schema satisfies the specification. Computing scientists develop mathematical and physical means to support or even enable that task. From this, the principal research questions of computing science may be derived. From this viewpoint, we try to propose a consistent set of notions together with a consistent terminology, which may clarify the relation of information technology and computing science to other scientific disciplines and also give rise to new ideas about computing science education. Keywords informatics, taxonomies, academic requirem..

Design of a PLC Program for VHS Case Study 1

This report presents our first results and conclusions with respect to - a simple specification formalism for hard real-time problems, - a method allowing to derive the specification of a control program in a systematic way from the properties of the plant to be controlled, - the application of the specification method, - the formal verification of the specification of a program for single batch operation with respect to the specification of the overall plant using PVS, - a control program for single batch operation written in SFC, - an informal verification of the specification of the program for multiple batch operation with respect to the specification of the overall plant using PVS, - extensions in the functionality of the control program in an informal way